Transistors, such as n-channel Field Effect Transistors (FET), formed in a Complementary-Metal-Oxide-Silicon (CMOS) integrated circuit operate when an input voltage is applied to a gate electrode. This gate voltage establishes an electric field perpendicular to a channel between a source and drain of the transistor. A conductance of the channel is controlled by the electric field. If no gate voltage is applied, a path between the source and drain is formed as two back-to-back pn junctions, and a drain current (I.sub.D) will be negligible. When a positive voltage is applied to the gate of the transistor, electrons are attracted to the channel. When the gate voltage exceeds a threshold level (V.sub.t), an inversion layer is formed in the channel to couple the source and drain. The threshold voltage level of a transistor is dependant upon several variables, both controllable and uncontrollable.
Relatively large threshold voltage variations from 0.4 to 0.6 Volts are common in current CMOS technology. This voltage variation is not compatible with lower power supply voltages implemented as the fabrication technology is scaled down to smaller dimensions. Power supply voltages of around one volt, or less, are required in integrated circuits fabricated with 0.1 micron CMOS technology. The statistical fluctuation of dopant atom concentrations in such sub-micron fabrication can be significant and contribute to threshold voltage fluctuations.
Different techniques have been described for self-compensation of threshold voltages in nMOS technology by applying a negative substrate bias. One technique, which can be applied in CMOS technology to compensate for V.sub.t fluctuation, includes a capacitor connected to the transistor gate which is charged to correct the threshold voltage variations. This circuit is illustrated in FIG. 1. A current source 10 is coupled to both the drain 12 and gate 14 (through switch 20) of the nMOSFET 16. A reference potential is coupled to the gate through a large capacitor 18 and switch 22. The capacitor is charged to a voltage required to maintain the current from the current source. This capacitor charge is retained while switches 20 and 22 are open and the transistor is connected only to the input signal at node 24. This charge must be refreshed periodically since it can leak away as leakage current in the transistor switches. Threshold voltage variations are thus compensated for by the charge temporarily stored on the capacitor. This technique is practical only for a few critical transistors in an integrated circuit because of the size of the capacitor required for each compensated transistor, such as transistors in a dynamic random access memory device (DRAM) sense amplifier. This capacitor can be implemented in DRAM technology using a stacked storage capacitor.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a transistor threshold voltage compensation circuit for low voltage integrated circuits which is not dependant upon the provision of a gate bias capacitor.